A NAND flash memory, featuring advantages of high capacity, low cost, and fast access, is extensively applied in various consumer electronic products. Apart from storing user data, a NAND flash memory is also frequently used in storage of memory space-consuming software data and programs, such as an operating system. However, constrained by a characteristic of a NAND flash memory that a single pin is assigned to serve both an address transmission port and a data transmission port there of boot procedure a controller in an electronic device using a NAND flash memory for storing software and codes is incapable of directly accessing the software and program codes from the NAND flash memory in a boot procedure. More specifically, only when a read command sequence is correctly sent, can the controller obtain data from the NAND flash memory; nevertheless, it remains a dilemma that the read command sequence is yet unknown to the controller during the boot procedure.
A read command sequence is determined according to capacity and a type of a NAND flash memory. As to current NAND flash memories, the read command sequence comes in four types: the first is a command 00 followed by a 3-byte address, the second is a command 00 followed by a 4-byte address, the third is a command 00 followed by a 4-byte address and then a command 30, and the fourth is a command 00 followed by a 5-byte address and then a command 30. The commands 00 and 30 are commands in hexadecimal representation, and the addresses of different lengths represent addresses of stored data to be read by the controller.
With respect to the issue that a controller is incapable of directly accessing software and codes from a NAND flash memory during a boot procedure, several solutions associated with the prior art are described as follows.
A first solution is to adopt a NOR flash memory for boot procedure. When an electronic device is powered on or reset, a controller therein first read a first segment of software program from the NOR flash memory to activate a corresponding hardware system (e.g., to set a DRAM memory controller), and then access subsequent software data and codes from the NAND flash memory. Content of the NOR flash memory can be modified repetitively, allowing a read command sequence applicable to the NAND flash memory to be written to the above-mentioned first segment of software program, so as to enable the controller to access the NAND flash memory accurately. However, this solution suffers from two shortcomings. One shortcoming is that the NOR flash memory is higher in cost that increases costs of the electronic device. The other shortcoming is that, it is necessary for the software program in the NOR flash memory to be correspondingly updated in the event that the electronic device manufacturer chooses to use NOR flash memories of other capacities due to variables such as inventory or material preparation reasons, which also infers to additional costs from manpower to time, and even a delay in product delivery.
One other current solution is to boot with a OneNand™ flash memory. The OneNand™ flash memory integrates a NAND flash memory chip, an SRAM chip and a logic chip into one single chip, and adopts a NOR flash memory interface. When the electronic device is powered on or reset, the OneNand™ flash memory enters a code reset mode upon detecting a voltage rising edge to relocate first 1000 bits of data in the NAND flash memory to the SRAM memory, so as to allow the controller to access the relocated data via the NOR flash memory. The above 1000 bits of data, representing a first segment of software program for initializing the hardware system, assist the controller to obtain subsequent software data and codes from the NAND flash memory to continue with the boot procedure. Again, this solution also suffers from two shortcomings. One shortcoming is that, the OneNand™ flash memory is similarly higher in cost that increases costs of the electronic device. The other shortcoming is that, in the event the electronic device manufacture decides to replace the OneNand™ flash memory with other types of memories, it is necessary for corresponding circuit board systems to be redesigned and again manufactured, meaning that flexibilities for hardware adjustments are greatly restricted.
There is yet another solution that adopts an eMMC memory for the boot procedure. An eMMC memory bundles a NAND flash memory with a controller chip, and communicates with an external processor through a MultiMediaCard interface. An eMMC memory of version 4.3 and onwards is equipped with a boot mode, which allows an external processor to read software data and codes from the eMMC memory required for the boot procedure. Similarly, this solution cannot escape from shortcomings of being high in cost and low in modification flexibilities. Furthermore, differences between response time after initialization of eMMC memories of different manufacturers increase design complexities of the controller.